Senior Layout Design Engineer
- Rijswijk, Zuid-Holland
- Vast
- Voltijds
- Lead top-level chip planning and execute block-level, sub-block, and custom layouts for CMOS and BiCMOS circuits
- Collaborate with remote design and layout teams across global time zones
- Perform schematic-driven layout with design constraints for high-performance, area-efficient designs
- Execute floor planning, power line planning, shielding, and device matching
- Perform DRC, LVS, and ERC verification using Cadence PVS or Mentor Calibre
- Contribute to chip-level integration, verification, and tape-out activities
- Support the development of layout standards and best practices across sites
- Mentor junior layout engineers and coordinate with offshore contractors
- Drive process improvements to ensure high-quality layout delivery
- 6 - 10 years of experience in analog and full-custom digital layout design
- Hands-on experience with TSMC 180nm, 65nm, and 22nm process technologies
- Proficient in Cadence Virtuoso layout environment
- Strong understanding of layout concepts such as parasitics, matching, crosstalk, EM, IR drop, latch-up, and isolation techniques
- Proven ability to meet area, power, and signal integrity constraints in complex designs
- Experience in chip-level planning and analog block integration
- Familiarity with design automation and productivity-enhancing scripting tools is a plus
- Detail-oriented, structured, and efficient in layout execution
- Track record of delivering high-quality work on time
- Self-driven, collaborative, and effective communicator
- Comfortable working in a dynamic, fast-paced team environment