
Internship: Exploring AI Algorithm Implementation on FPGA
- Eindhoven, Noord-Brabant
- Training
- Voltijds
Most AI models are developed and trained in high-level environments like Python and C++. Traditional FPGA development, using VHDL or Verilog, poses a barrier to rapidly deploying such models.Emerging toolchains now support flows where trained models can be translated into synthesizable logic using high-level languages or model conversion frameworks. This assignment challenges the student to explore the state of the art in AI-on-FPGA inference, evaluate implementation options, and build a working prototype using a simple AI algorithm.You’re role
1. Research & Landscape Analysis
- Investigate the AI inference capabilities of the FPGA platforms used in medical imaging systems, focusing on hardware features such as DSP blocks, memory hierarchies, and parallel processing units.
- Conduct a survey of available toolchains and frameworks (e.g., Vitis AI, FINN, hls4ml, Brevitas, ONNX, Deep Learning IP cores) that enable mapping of pre-trained AI models to FPGA hardware.
- Summarize state-of-the-art trends in AI-on-FPGA deployment, with an emphasis on their relevance to real-time, safety-critical medical imaging applications.
- Perform a comparative study of FPGA development flows for AI inference:
- Low-level RTL (VHDL/Verilog)
- High-Level Synthesis (C++/SystemC)
- Model-to-hardware compilers and frameworks (e.g., FINN, hls4ml).
- Evaluate which types of AI models (e.g., quantized CNNs, MLPs, statistical algorithms) are most feasible for FPGA deployment.
- Assess common optimization techniques (quantization, pruning, fixed-point arithmetic) and their impact on resource usage, latency, and accuracy.
- Select a representative AI algorithm or lightweight statistical method relevant to medical image enhancement (e.g., noise reduction filter, basic classifier, or histogram-based analysis).
- Implement the algorithm, synthesize it to FPGA, where relevant, experiment with modern AI-to-FPGA frameworks.
- Optimize the design to balance accuracy, speed, and hardware efficiency.
- Integrate the implemented algorithm into a test pipeline with real or representative image data.
- Demonstrate functionality on FPGA hardware.
- Present a comprehensive evaluation covering performance, latency, resource usage, and feasibility for use in real-time medical imaging workflows.
- Provide recommendations for future work, highlighting opportunities for scaling to more complex AI models or clinical use cases.
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